A Programmable Low Jitter Clock Source to 900MHz

A Low Jitter Variable Rate Clock Generator to 1000 MHz

Features

The requirements for this clock generator were originally driven by a need to supply a AD9913 DDS with a good quality clock signal in the 250 MHz range. The design presented here should also be useful in other applications where a low jitter clock source is required up to 1000 MHz.

Good jitter and phase noise performance with RMS jitter being ∼ 0.5 ps.
Produces a selection of CMOS, LVDS, LVPECL clock signals.
Agile frequency selection. The AD9552 is based on a fractional-N phase locked loop design with the intention of replacing high frequency crystal oscillators and resonators.
Preset output frequency selection using on board switch configuration.
Reference switchable between on-board and external sources.
Full configurability of output signal characteristics is available via software (SPI) control.
Up to four clock outputs with CMOS clock signals or two clock outputs with LVPECL or LVDS.
Single supply operation with low power (< 400 mW in most cases)
Design files available at https://gitlab.com/dyadic-groups/rfblocks-hardware-modules/clockgenerator_2 (licensed under CERN-OHL-S v2).

Typical Performance Characteristics

Output modes

250MHz output — **Figure 3a**: Typical output waveforms at 250 MHz.

50MHz output — **Figure 3b**: Typical output waveforms at 50 MHz.

Output power

Figures 4a and 4b show the rolloff in signal output power as a function of frequency. At lower frequencies the fundamental peak power is less than the measured integrated power. This is expected since the measured integrated power will include the power in the harmonics of the signal out to the effective bandwidth of the power detector used to take the measurements. As the clock output frequency increases the number of harmonics within this bandwidth will drop. This effect is particularly noticable for the CMOS (strongly driven) mode due to the substantially higher power output in this mode.

Integ. Pwr — **Figure 4a**: Integrated power output.

Fund. Pwr — **Figure 4b**: Fundamental peak power.

Figure 5 shows the inbalance in the integrated power output from the positive and negative pins of a given clock generator channel. Measurement of the peak power of the signal output shows no imbalance. These observations can be reconciled by noticing that the duty cycle variations for both LVDS and LVPECL output modes is quite wide (40 to 60%). The measured imbalance in the integrated power output is therefore a measure of the actual duty cycle of the signal. The duty cycle of the CMOS mode (at least for the strongly driven configuration) is more tightly controlled and the imbalance is therefore somewhat less.

Pwr imbal. — **Figure 5**: Output power imbalance.

Phase noise and jitter

Calculations of the integrated jitter using AN3359.pdf and AN3359-example.xls and based on the phase noise specifications in the AD9552 datasheet indicate approximately 550 fS of jitter. This is relatively constant across the frequency range.

Applications Information

Figure 9 illustrates the minimal setup for controlling the clock generator board. The board is connected to the atmega USB controller which is running the ECApp embedded control firmware. Clock generator board pins are described in Table 1.

minimal_clkgen — **Figure 9**: Minimal Clock Generator Control

The rfblocks Python package provides the AD9552Controller class which is used to control the board. The following code snippet shows a small example:

>>> from rfblocks import ad9552, AD9552Controller, create_serial

>>> ser_device = '/dev/tty.usbmodem14101'
>>> ser = create_serial(ser_device)

>>> clk = ad9552('D3', 'C5', None, 10.0)

>>> ctl = AD9552Controller('ClkControl', clk)
>>> ctl.initialize(ser)
True

>>> ctl.freq = 124.0
>>> ctl.channels['1'].state = ad9552.OutputState.ACTIVE
>>> ctl.channels['1'].mode = ad9552.OutputMode.LVDS
>>> locked = ctl.configure(ser)
>>> locked
True

>>> ctl.freq = 644.12
>>> locked = ctl.configure_freq(ser)
>>> locked
True

The code does the following:

Import the rfblocks AD9552Controller and ad9552 classes.
Open the USB/RS-232 serial device which connects the host computer to the ECApp control firmware running on the controller board.
Create an instance of the ad9552 device class. The clock generator board's chip select (CS) pin is connected to the atmega controller PD0 pin, the boards PLL lock status pin (Locked) is connected to the controller's PC4 pin. The clock generator board's reset pin is left unconnected and the reference frequency is 10.0 MHz.
Create an instance of AD9552Controller and initialize the clock generator board hardware. The default state of the board after initialization is both clock channels powered down with output mode set to LVPECL. The default output frequency of the board is set to 250 MHz. The AD9552Controller initialize method returns the PLL lock status as a boolean, True indicating that the PLL is locked.
Set the output frequency of the board to 124 MHz. Set the state of channel 1 of the generator to active with an output mode of LVDS. The call to the AD9552Controller configure method pushes the state changes to the board hardware. The boolean value returned by configure gives the clock generator PLL lock status after the state change.
If only the clock generator frequency is being changed then the AD9552Controller configure_freq method is used to update the board. The boolean value returned by configure_freq indicates the PLL lock status after the frequency is changed.

Board connector configuration

**Table 1**. Board pin configuration and function descriptions
Board Pin	Type	Description
`SDIO`	Input/Output	Serial control data
`SCLK`	Input	Serial control data clock
`~CS`	Input	Chip select signal. Active low
`Reset`	Input	Digital input, active high. Note that this signal
		is pulled high on the AD9552 so the default state
		of the device is reset. The Reset pin can be tied
		directly to ground if reset control is not required.
`Ref`	Input	Digital input. This pin is pulled high on the board
		so the default state is clk ref. = on board 10MHz
		oscillator. Setting the pin to logic 0 will select
		clk ref. = external reference (via `J12`).
`Locked`	Output	Active high PLL locked status. This pin will be
		high when the clock generator PLL is locked and the
		output signal frequency is stable.
`5V`	Power Input	Clock generator 5V DC power input.
`Gnd`	Power Input	Clock generator module ground.
`REF`	Signal Input	Female MMCX connector for external clock generator
		reference signal input.
`Out1`	Signal Output	Female MMCX connectors for differential square wave
		clock outputs, channel 1.
`Out2`	Signal Output	Female MMCX connectors for differential square wave
		clock outputs, channel 2.

Conn. layout — **Figure 10**: Clock generator module connector layout.

Reference Designs

Design Notes

Schematic

Figure 11 shows the schematic design for the clock generator.

The three 0Ω resistors R14, R15, and R16 allow the configuration of the input reference frequency control pins A0, A1, and A2. (These pins have internal 100k pullups on the AD9552.) Table 9 in the AD9552 datasheet shows the eight reference frequencies and the associated values of the control pins. The table is reproduced here for convenience. An on board reference frequency of 10 MHz is used (configured by populating R14, R15, and R16 with 0Ω links). This then requires any external reference used to also be 10 MHz.

**Table 2**. Input Reference Frequency Selection Pins
A2	A1	A0	Reference Frequency (MHz)
0	0	0	10.00
0	0	1	12.00
0	1	0	12.80
0	1	1	16.00
1	0	0	19.20
1	0	1	19.44
1	1	0	20.00
1	1	1	26.00

SW 1 allows the selection of one of the preset frequency translation ratios as documented in Table 10 of the AD9552 datasheet. In addition, it also allows the selection of either LVDS or LVPECL signal levels for both of the signal outputs (when the signal outputs are not under SPI control).

The output signals are routed through networks which can be be configured for matching and/or biasing of LVDS and LVPECL in various modes (see https://www.idt.com/us/en/document/apn/lvds-pecl-termination-app-note).

Power is provided by an LP5907 low noise linear regulator (output voltage noise < 6.5 \(\mu\)V RMS). Input to the regulator is protected from overvoltage with a 5.6V zener, D1, and low pass filtered with the combination of C13, R11, and C14. The LP5907 PSRR is at least 40 dB down up to approximately 1 Mhz. The low pass filter is 20 dB down at approximately 1.5 MHz. The two together ensure that any power line interference is attenuated by at least 40 dB.

Layout

Figure 12 illustrates the block level organization of the clock generator PCB layout.

External reference

The AD9552 can handle an external reference with an offset of up to about 700 mV. This offset would be dictated by the actual value of the reference clock maximum input low voltage. For reliable operation the nominal external reference should be 0 to 2V into approximately 100 k \(\Omega\).

Scripts

measuring fundamental power output

Figure 13 illustrates the test setup used to measure the clock generator fundamental power output. The ClockGen app is used to control the clock generator and is started prior to running the script:

python clkgen.py -d /dev/cu.usbmodem141401 &
# ...

Note that the command serial device is specified on the command line (rather than selected from the Control Port drop down list of the running app). The app can be run 'headless' (that is, without any on-screen UI) by specifying the --nogui command line option.

Clkgen Fund. Pwr Test — **Figure 13**: Clock generator fundamental power output test setup.

#
# Generated from ad9552.org
#
import sys
from time import sleep
import json
import numpy as np
from scipy import (
    interpolate
)
import rpyc
from rfblocks import (
    ad9552, DividerRangeException
)
from tam import (
    InstrumentMgr, InstrumentInitializeException,
    UnknownInstrumentModelException, DSA815_ID,
    DSG815_ID
)

chan_id = '2'
measurements_file = 'ad9552-output-fund-pwr.json'
loss_fn = None

def insertion_loss(freq):
    return float(loss_fn(freq))

def measure_sigpwr():
    sig_pwr = {}
    for f in freq_list:
        clkmod2.freq = f
        pll_lock = clkgen.root.configure_freq('clkmod2')
        sleep(0.5)
        if pll_lock is True:
            pwr, _ = sa.measure_pwr(f)
            sig_pwr['{:.1f}'.format(f)] = pwr + insertion_loss(f)
    return sig_pwr

def calibrate(srcpwr, start_freq, stop_freq, step_freq):
    loss = {}
    sg.output = True
    for f in np.arange(start_freq, stop_freq, step_freq):
        # Note that the property assignment here may actually
        # be a rpyc remote operation depending on the selected
        # calibration device.  Since ~f~ (and possibly ~srcpwr~)
        # may be numpy array scalars it is necessary to explicitly
        # cast these to standard Python float values.  If this is
        # not done the remote rpyc process will almost certainly
        # generate strange numpy related exceptions.
        sig_freq = float(f)
        sg.freq = sig_freq
        sg.level = float(srcpwr)
        meas_pwr, _ = sa.measure_pwr(sig_freq)
        loss[sig_freq] = srcpwr - meas_pwr
    sg.output = False
    freqs = np.array([f for f in loss.keys()])
    loss_arr = np.array([v for v in loss.values()])
    loss_interp_fn = interpolate.interp1d(
        freqs, loss_arr, kind='cubic')
    return loss_interp_fn

# Clock generator initialization
try:
    clkgen = rpyc.connect("127.0.0.1", 18861)
except ConnectionRefusedError:
    print("Can't connect to the clkgen app - is it running?")
    sys.exit(-1)
clkgen.root.initialize()
clk_ctls = clkgen.root.controllers()
clkmod2 = clk_ctls['clkmod2']
chan = clkmod2.channels[chan_id]

# Spectrum analyzer initialization
instrument_mgr = InstrumentMgr()
try:
    sa = instrument_mgr.open_instrument('DSA815', DSA815_ID)
    sg = instrument_mgr.open_instrument('DSG815', DSG815_ID)
except InstrumentInitializeException as iie:
    print(iie.message)
    sys.exit(-2)
except UnknownInstrumentModelException as ume:
    print(ume.message)
    sys.exit(-3)

sa.vavg = 2
sa.fspan = 0.1
sa.ref_level = 10.0

print("""Calibration of the test cable must now be carried out.
Please connect the test cable between the RF output
of the DSG815 signal generator and the DSA815 spectrum analyzer.""")
input("Press a key when ready... ")

loss_fn = calibrate(0.0, 10.0, 1100.0, 50.0)

print("""Calibration complete.
Please connect the test cable between the Clk{}+ output
of the Clock Generator and the input of the DSA815
spectrum analyzer.""".format(chan_id))
input("Press a key when ready... ")

# ------------------------------------------------------------
#
# CMOS output mode measurement
#
freq_list = [float(f) for f in np.linspace(20.0, 500.0, 40).round()]

chan.mode = ad9552.OutputMode.CMOS_BOTH_ACTIVE
chan.drive = ad9552.DriveStrength.STRONG
chan.state = ad9552.OutputState.ACTIVE
pll_lock = clkgen.root.configure('clkmod2')

sa.fspan = 0.1
sa.ref_level = 20.0
cmos_strong = measure_sigpwr()

chan.drive = ad9552.DriveStrength.WEAK
pll_lock = clkgen.root.configure('clkmod2')

sa.ref_level = 10.0
cmos_weak = measure_sigpwr()

# ------------------------------------------------------------
#
# LVPECL and LVDS output mode measurement
#

# The AD9552 can't generate frequencies between 810 and 838 MHz.
# This is because there is no integer value output divide factor
# for these frequencies given the max. and min. VCO frequencies
# for the AD9552.  When generating the list of output signal
# frequencies and frequency in this range is removed from the list.
farr = np.linspace(50.0, 1000.0, 41).round()
freq_list = [float(f) for f in farr[(farr < 811) | (farr > 838)]]

chan.mode = ad9552.OutputMode.LVPECL
chan.drive = ad9552.DriveStrength.STRONG
chan.state = ad9552.OutputState.ACTIVE
pll_lock = clkgen.root.configure('clkmod2')

lvpecl = measure_sigpwr()

chan.mode = ad9552.OutputMode.LVDS
chan.drive = ad9552.DriveStrength.STRONG
chan.state = ad9552.OutputState.ACTIVE
pll_lock = clkgen.root.configure('clkmod2')

lvds_strong = measure_sigpwr()

chan.drive = ad9552.DriveStrength.WEAK
pll_lock = clkgen.root.configure('clkmod2')

lvds_weak = measure_sigpwr()

# -----------------------------------------------------------
#
# Clean up and save the measurement results
#

chan.state = ad9552.OutputState.POWERED_DOWN
pll_lock = clkgen.root.configure('clkmod2')

clkgen.close()

measurements = {'cmos-weak': cmos_weak,
                'cmos-strong': cmos_strong,
                'lvpecl': lvpecl,
                'lvds-weak': lvds_weak,
                'lvds-strong': lvds_strong}

with open(measurements_file, 'w') as fd:
    json.dump(measurements, fd)

Measuring integrated power output

Figure 14 illustrates the test setup used to measure the clock generator integrated power output. The PowerMeter app is used to control the power meter and the ClockGen app is used to control the clock generator. Both of these apps are started prior to running the script:

python pwrmeter.py -d /dev/cu.usbmodem141301 &
# ...
python clkgen.py -d /dev/cu.usbmodem141401 &
# ...

Note that the command serial device is specified on the command line (rather than selected from the Control Port drop down list of the running app). The apps can be run 'headless' (that is, without any on-screen UI) by specifying the --nogui command line option.

Clkgen Integ. Pwr Test — **Figure 14**: Clock generator integrated power output test setup.

The 30 dB attenuator is required in order to bring the clock generator output signal within the range of linear measurement for the power meter. The power meter/attenuator combination is calibrated prior to taking measurements of the clock generator power output. This necessitates physically moving the power meter measurement head/attenuator between the calibration signal generator and the test clock generator output. Previously measured calibration data may also be loaded from file.

#
# Generated from ad9552.org
#
import sys
from time import sleep
import json
import numpy as np
import rpyc
from rfblocks import ad9552, DividerRangeException
from tam import DSG815_ID

measurements_file = 'ad9552-output-pwr.json'
lt5537_cal_file = '30dB-atten-20-500MHz.json'
ltc5582_cal_file = '30dB-atten-50-1000MHz.json'

def measure_sigpwr(pwr_chan):
    sig_pwr = {}
    for f in freq_list:
        clkmod2.freq = f
        pll_lock = clkgen.root.configure_freq('clkmod2')
        sleep(0.5)
        if pll_lock is True:
            chan_controllers[pwr_chan].freq = f
            pwrmeter.root.measure(pwr_chan)
            sig_pwr['{:.1f}'.format(f)] = \
                float(chan_controllers[pwr_chan].pwr)
    return sig_pwr

def calibrate(pwr_chan, start_freq, stop_freq, step_freq):
    # Power meter/attenuator calibration (see Note 1 below).
    # The power meter measurement head/attenuator must be connected
    # to the DSG815 signal output prior to executing the following.
    old_timeout = pwrmeter._config['sync_request_timeout']
    pwrmeter._config['sync_request_timeout'] = None

    # The calibrate function has quite a few parameters - it makes
    # it easier to keep track of things to use a dict:
    cal_params = dict(
        ctl_id=pwr_chan, src_dev='DSG815', device_id=DSG815_ID,
        src_chan=0, srcpwr=0.0,
        startf=start_freq, stopf=stop_freq, stepf=step_freq
    )
    status = pwrmeter.root.calibrate(**cal_params)
    pwrmeter._config['sync_request_timeout'] = old_timeout
    if pwrmeter.root.calstatus[1] != 0:
        print('Calibration failed: {}'.format(status))

# Clock generator initialization
try:
    clkgen = rpyc.connect("127.0.0.1", 18861)
except ConnectionRefusedError:
    print("Can't connect to the clkgen app. Is it running?")
    sys.exit(-1)
clkgen.root.initialize()
clk_ctls = clkgen.root.controllers()
clkmod2 = clk_ctls['clkmod2']
chan2 = clkmod2.channels['2']

# Power meter initialization
try:
    pwrmeter = rpyc.connect('127.0.0.1', 18863)
except ConnectionRefusedError:
    print("Can't connect to the pwrmeter app. Is it running?")
    sys.exit(-2)
pwrmeter.root.initialize()
pwrmeter.root.detector_enable(0, False)
chan_controllers = pwrmeter.root.detectors
chan_ctl1 = chan_controllers[1]

# ------------------------------------------------------------
#
# CMOS output mode measurement
#
freq_list = [float(f) for f in np.linspace(20.0, 500.0, 40).round()]

if lt5537_cal_file is None:
    print("""Please connect the LT5537 power meter measurement
head to the RF output of the DSG815 signal generator.""")
    input("Press a key when ready... ")
    calibrate(1, 5.0, 550.0, 20.0)
    # Calibration data can be saved to a file for later use.
    lt5537_cal_file = "30dB-atten-20-500MHz.json"
    pwrmeter.root.save_caldata(1, lt5537_cal_file)
    print("Calibration complete.")
else:
    # An alternative to carrying out repeated calibration
    # operations is to load previously saved calibration data.
    # The file path will be relative to the directory in which
    # the power meter app was started.
    pwrmeter.root.load_caldata(1, "30dB-atten-20-500MHz.json")

chan_ctl1.apply_correction = True

print("""Please connect the LT5537 power meter measurement
head to the Clk2+ output of the Clock Generator.""")
input("Press a key when ready... ")

# The drive strength for CMOS can be either WEAK or STRONG
chan2.mode = ad9552.OutputMode.CMOS_BOTH_ACTIVE
chan2.drive = ad9552.DriveStrength.STRONG
chan2.state = ad9552.OutputState.ACTIVE
pll_lock = clkgen.root.configure('clkmod2')
cmos_strong = measure_sigpwr(pwr_chan=1)

chan2.drive = ad9552.DriveStrength.WEAK
pll_lock = clkgen.root.configure('clkmod2')
cmos_weak = measure_sigpwr(pwr_chan=1)

# ------------------------------------------------------------
#
# LVPECL and LVDS output mode measurement
#

# The AD9552 can't generate frequencies between 810 and 838 MHz.
# This is because there is no integer value output divide factor
# for these frequencies given the max. and min. VCO frequencies
# for the AD9552.  When generating the list of output signal
# frequencies and frequency in this range is removed from the list.
farr = np.linspace(50.0, 1000.0, 41).round()
freq_list = [float(f) for f in farr[(farr < 811) | (farr > 838)]]

pwrmeter.root.detector_enable(1, False)
pwrmeter.root.detector_enable(0, True)
chan_ctl0 = chan_controllers[0]

# Now the power meter measurement head is changed to
# the LTC5582 power sensor on channel 0.  This gives a measurement
# range of 0.1 to 6GHz.  The calibration range in this
# instance will be 50 to 1000MHz.
if ltc5582_cal_file is None:
    print("""Please connect the LT5582 power meter measurement
head to the RF output of the DSG815 signal generator.""")
    input("Press a key when ready... ")
    calibrate(1, 50.0, 1000.0, 50.0)
    # Calibration data can be saved to a file for later use.
    ltc5582_cal_file = "30dB-atten-50-1000MHz.json"
    pwrmeter.root.save_caldata(0, ltc5582_cal_file)
    print("Calibration complete.")
else:
    # An alternative to carrying out repeated calibration
    # operations is to load previously saved calibration data.
    # The file path will be relative to the directory in which
    # the power meter app was started.
    pwrmeter.root.load_caldata(0, ltc5582_cal_file)

chan_ctl0.apply_correction = True

print("""Please connect the LTC5582 power meter measurement
head to the Clk2+ output of the Clock Generator.""")
input("Press a key when ready... ")

chan2.mode = ad9552.OutputMode.LVPECL
chan2.drive = ad9552.DriveStrength.STRONG
chan2.state = ad9552.OutputState.ACTIVE
pll_lock = clkgen.root.configure('clkmod2')
lvpecl = measure_sigpwr(pwr_chan=0)

# The drive strength for LVDS can be either WEAK or STRONG
chan2.mode = ad9552.OutputMode.LVDS
chan2.drive = ad9552.DriveStrength.STRONG
chan2.state = ad9552.OutputState.ACTIVE
pll_lock = clkgen.root.configure('clkmod2')
lvds_strong = measure_sigpwr(pwr_chan=0)

chan2.drive = ad9552.DriveStrength.WEAK
pll_lock = clkgen.root.configure('clkmod2')
lvds_weak = measure_sigpwr(pwr_chan=0)

# -----------------------------------------------------------
#
# Clean up and save the measurement results
#

chan2.state = ad9552.OutputState.POWERED_DOWN
pll_lock = clkgen.root.configure('clkmod2')

clkgen.close()

measurements = {'cmos-weak': cmos_weak,
                'cmos-strong': cmos_strong,
                'lvpecl': lvpecl,
                'lvds-weak': lvds_weak,
                'lvds-strong': lvds_strong}

with open(measurements_file, 'w') as fd:
    json.dump(measurements, fd)

See Power meter calibration and correction for details of the calibration process for the power meter.

Appendix

**Table A1**: Output Frequency Selection Pins (a reproduction of Table 10 in the AD9552 datasheet)
Y5	Y4	Y3	Y2	Y1	Y0	VCO Frequency (MHz)	Output (MHz)
0	0	0	0	0	0	3732.48	51.84
0	0	0	0	0	1	3888	54
0	0	0	0	1	0	3840	60
0	0	0	0	1	1	3932.16	61.44
0	0	0	1	0	0	3750	62.5
0	0	0	1	0	1	3733.296	66.666
0	0	0	1	1	0	3560.439	74.17582
0	0	0	1	1	1	3564	74.25
0	0	1	0	0	0	3732.48	77.76
0	0	1	0	0	1	3932.16	98.304
0	0	1	0	1	0	4000	100
0	0	1	0	1	1	3825	106.25
0	0	1	1	0	0	3840	120
0	0	1	1	0	1	4000	125
0	0	1	1	1	0	3724	133
0	0	1	1	1	1	3732.48	155.52
0	1	0	0	0	0	3750	156.25
0	1	0	0	0	1	3825	159.375
0	1	0	0	1	0	3867.188	161.1328125
0	1	0	0	1	1	3944.531	10518.75/64
0	1	0	1	0	0	3999.086	155.52 × (15/14)
0	1	0	1	0	1	4015.959	155.52 × (255/237)
0	1	0	1	1	0	4023.878	167.6616
0	1	0	1	1	1	3554.742	177.7371
0	1	1	0	0	0	3932.16	245.76
0	1	1	0	0	1	4000	250
0	1	1	0	1	0	3732.48	311.04
0	1	1	0	1	1	3840	320
0	1	1	1	0	0	4000	400
0	1	1	1	0	1	3471.4	433.925
0	1	1	1	1	0	3718.75	531.25
0	1	1	1	1	1	3763.2	537.6
1	0	0	0	0	0	3984.375	569.1964
1	0	0	0	0	1	3732.48	622.08
1	0	0	0	1	0	3748.229	624.7048
1	0	0	0	1	1	3750	625
1	0	0	1	0	0	3763.978	622.08 × (239/237)
1	0	0	1	0	1	3779.927	629.9878
1	0	0	1	1	0	3840	640
1	0	0	1	1	1	3849.12	641.52
1	0	1	0	0	0	3867.188	625 × (66/64)
1	0	1	0	0	1	3944.531	657.421875
1	0	1	0	1	0	3961.105	657.421875 × (239/238)
1	0	1	0	1	1	3999.086	622.08 × (15/14)
1	0	1	1	0	0	4014.769	669.1281
1	0	1	1	0	1	4015.959	622.08 × (255/237)
1	0	1	1	1	0	4017.857	625 × (15/14)
1	0	1	1	1	1	4025.032	670.8386
1	1	0	0	0	0	4032.976	622.08 × (255/236)
1	1	0	0	0	1	3452.846	625 × (66/64) × (15/14)
1	1	0	0	1	0	3467.415	625 × (255/237) × (66/64)
1	1	0	0	1	1	3468.75	693.75
1	1	0	1	0	0	3481.996	622.08 × (253/226)
1	1	0	1	0	1	3521.903	657.421875 × (255/238)
1	1	0	1	1	0	3536.763	657.421875 × (255/237)
1	1	0	1	1	1	3582.686	716.5372
1	1	1	0	0	0	3593.75	718.75
1	1	1	0	0	1	3598.672	719.7344
1	1	1	0	1	0	3740.355	748.0709
1	1	1	0	1	1	3750	750
1	1	1	1	0	0	3888	777.6
1	1	1	1	0	1	3897.843	779.5686
1	1	1	1	1	0	3906.25	781.25
1	1	1	1	1	1	4028.32	625 × (10/8) × (66/64)