hmc833

class rfblocks.hmc833(sen: str | None = None, ld_sdo: str | None = None, ref: str | None = None, fref: float = 50.0, refdiv: int = 1, refsrc: ReferenceSource = ReferenceSource.INTERNAL, cp_gain: int = 100)[source]

Encapsulates control for the HMC833 frequency synthesizer device.

Documentation for the HMC833 frequency synthesizer rfblocks module can be found here: An HMC833 Frequency Synthesizer

Parameters:

  • sen (str) – The HMC833 serial port enable (SEN) controller pin.

  • ld_sdo (str) – The HMC833 lock detect and GPO serial output controller pin.

  • ref (str) – The PLO board reference select controller pin.

  • fref (float) – The input reference frequency in MHz. Default: 50 MHz.

  • refdiv (int) – The input reference divider value (1..16,383), default 1.

  • refsrc – The PLO reference source.

  • type – hmc833.ReferenceSource

DIVIDER_VALUES: List[int] = [2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62]

Legal RF output divider values

class DividerGain(value)[source]

An enum containing possible gain settings for the divider output stage. (ad9552.DividerGain.MAXGAIN_MINUS_3DB, ad9552.DividerGain.MAXGAIN)

MAX_DIVIDER: int = 62

Maximum RF output divider value

MAX_FREQUENCY: float = 6000.0

The maximum synthesizer output frequency

MAX_FUNDAMENTAL: float = 3000.0

The maximum VCO fundamental frequency

MIN_FREQUENCY: float = 25.0

The minimum synthesizer output frequency

MIN_FUNDAMENTAL: float = 1500.0

The minimum VCO fundamental frequency

class OutputBufferGain(value)[source]

An enum containing possible gain settings for the device output buffer. (ad9552.OutputBufferGain.MAXGAIN_MINUS_9DB, ad9552.OutputBufferGain.MAXGAIN_MINUS_6DB, ad9552.OutputBufferGain.MAXGAIN_MINUS_3DB, ad9552.OutputBufferGain.MAXGAIN)

class ReferenceSource(value)[source]

An enum containing the possible settings for the reference source. (hmc833.ReferenceSource.INTERNAL, hmc833.ReferenceSource.EXTERNAL)

auto_gain(fout: float) → None[source]

Set the buf_gain and div_gain based on the specified output frequency.

This method will adjust the output buffer and divider output buffer gains for optimal power flatness across all output frequencies (from 25 to 6000 MHz).

Parameters:

fout (float) – The device output frequency in MHz.

Note

Invoking this method will set appropriate values for buf_gain and div_gain. The config_gain method should then be called in order to generate a command which can be used to configure the gain settings on the actual device.

See also

buf_gain() div_gain() config_gain()

>>> plo1 = hmc833('d1', 'c5')
>>> plo1.auto_gain(560)
>>> plo1.buf_gain
<OutputBufferGain.MAXGAIN_MINUS_9DB: 0>
>>> plo1.div_gain
<DividerGain.MAXGAIN: 1>
>>> plo1.auto_gain(1560)
>>> plo1.buf_gain
<OutputBufferGain.MAXGAIN_MINUS_9DB: 0>
>>> plo1.div_gain
<DividerGain.MAXGAIN_MINUS_3DB: 0>
>>> plo1.auto_gain(2560)
>>> plo1.buf_gain
<OutputBufferGain.MAXGAIN_MINUS_3DB: 2>
>>> plo1.div_gain
<DividerGain.MAXGAIN_MINUS_3DB: 0>
>>> plo1.auto_gain(3560)
>>> plo1.buf_gain
<OutputBufferGain.MAXGAIN_MINUS_3DB: 2>
>>> plo1.div_gain
<DividerGain.MAXGAIN_MINUS_3DB: 0>
>>> plo1.auto_gain(4560)
>>> plo1.buf_gain
<OutputBufferGain.MAXGAIN: 3>
>>> plo1.div_gain
<DividerGain.MAXGAIN_MINUS_3DB: 0>
property buf_gain: OutputBufferGain

The output buffer gain setting.

check_is_locked() → str[source]

Check if the device PLL is locked.

Returns:

The command string for checking the device PLL lock status.

chip_reset() → str[source]

Reset the chip internal logic to default states.

Returns:

The command for reseting the PLL subsystem SPI registers.

From Section 1.13 of the HMC833 data sheet: The HMC833LP6GE features a hardware Power on Reset (POR). All chip registers will be reset to default states approximately 250 us after power up.

The PLL subsystem SPI registers may also be soft reset by an SPI write to register rst_swrst (Reg_00h). Note that the soft reset does not clear the SPI mode of operation referred to in section 1.17.2. The soft reset is applied by writing Reg_00h[5]=1. The reset is a one time event that occurs immediately. The reset bit does not have to be returned to 0 after a reset. It should be noted that the VCO subsystem is not affected by the PLL soft reset. The VCO subsystem registers can only be reset by removing the power supply.

>>> plo1 = hmc833('d1', 'c5')
>>> plo1.chip_reset()
'W00,00,20,00:HD1:LD1:'
config_analog_enables()[source]

Configure the ‘analog enables register’ (Reg_08h).

Returns:

The command string required to set PLO Reg_08h.

config_autocal()[source]

Configure the ‘autocal register’ (Reg_0Ah).

Returns:

The command string required to set PLO Reg_0Ah.

config_chargepump(sd_mod_en: bool) → str[source]

Configure the PLO sigma/delta modulator.

Parameters:

en (bool) – True for enabling the SD modulator. False to disable.

Returns:

The command string required to effect the register initialization.

config_device_state() → None[source]

Configure the device state.

Set Reg_01h[0] (rst_chipen_pin_select) to 0 in order to control PLL enable via SPI. PLL enable is then controlled using Reg_01h[1] (rst_chipen_from_spi) subject to masking using the bits in Reg_01h[2:7].

If AutoRFO mode is enabled (via VCO_Reg_03h[2] = 0) as recommended in the HMC833 datasheet, then the VCO subsystem is powered up/down by setting VCO_Reg_01h[0] (Master enable VCO subsystem) to 0b1 and 0b0 respectively. If AutoRFO mode is disabled (via VCO_Reg_03h = 1) then the VCO subsystem is powered down by setting VCO_Reg_01h[0] = 0 and setting VCO_Reg_01h[0] = 1 will power up the various VCO subsystem components subject to the setting of the associated bit in VCO_Reg_01h. In short, it’s best to go with the recommended AutoRFO enabled setting in VCO_Reg_03h

Note

Not currently implemented.

config_frequency(fout: float, full_reg_update: bool = False) → str[source]

Configure for a specified output frequency

When configuring the PLO registers for a specified frequency we try to minimize the number of register updates in order to reduce the time taken to effect the changes. This optimization process produces incorrect results in some circumstances, for example when the PLO reference divider is changed. In cases such as this the ~full_reg_update~ should be set to ~True~ in order to update all relevant PLO registers when configuring the output frequency.

Parameters:

  • fout (float) – The required output frequency in MHz.

  • reset_state (bool) – Force an update of the relevant device registers.

Returns:

The command string required to effect the specified frequency output.

>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)
>>> plo2.device_initialize(1000.0)
'W00,00,20,00:HD2:LD2:LB5:W00,00,02,08:HD2:LD2:W00,00,04,10:HD2:LD2:W00,01,88,28:HD2:LD2:W00,16,28,28:HD2:LD2:W00,60,A0,28:HD2:LD2:W00,01,10,28:HD2:LD2:W00,08,98,28:HD2:LD2:W00,00,00,28:HD2:LD2:W03,07,CA,30:HD2:LD2:W19,32,64,48:HD2:LD2:W00,21,4d,38:HD2:LD2:WC1,BE,FF,40:HD2:LD2:W00,40,46,50:HD2:LD2:W07,C0,61,58:HD2:LD2:W00,00,C1,78:HD2:LD2:W00,00,20,18:HD2:LD2:W00,00,00,20:HD2:LD2:'
>>> plo2.config_frequency(512.0)
'W00,02,10,28:HD2:LD2:W00,00,00,28:HD2:LD2:W03,0F,4A,30:HD2:LD2:W59,32,64,48:HD2:LD2:W00,21,4d,38:HD2:LD2:WC1,BE,FF,40:HD2:LD2:W00,40,46,50:HD2:LD2:W07,C0,61,58:HD2:LD2:W00,00,C1,78:HD2:LD2:W00,00,20,18:HD2:LD2:Wc4,9b,a6,20:HD2:LD2:'
>>> plo2.config_frequency(764.0)
'W00,01,10,28:HD2:LD2:W00,00,00,28:HD2:LD2:W00,00,18,18:HD2:LD2:W72,b0,21,20:HD2:LD2:'
>>> plo2.config_frequency(500.0)
'W00,03,10,28:HD2:LD2:W00,00,00,28:HD2:LD2:W03,07,CA,30:HD2:LD2:W19,32,64,48:HD2:LD2:W00,21,4d,38:HD2:LD2:WC1,BE,FF,40:HD2:LD2:W00,40,46,50:HD2:LD2:W07,C0,61,58:HD2:LD2:W00,00,C1,78:HD2:LD2:W00,00,30,18:HD2:LD2:W00,00,00,20:HD2:LD2:'
>>> plo2.config_frequency(1000.0)
'W00,01,10,28:HD2:LD2:W00,00,00,28:HD2:LD2:W00,00,20,18:HD2:LD2:'
config_frequency_registers(nint: int, nfrac: int) → str[source]

Configure the device registers for the specified fractional divide ratio

Parameters:

  • nint (19-bit int (20 to 524,284)) – The integer part of the frequency tuning.

  • nfrac (24-bit int (0 to 2^24)) – The fractional part of the frequency tuning.

Returns:

The command string required to set the necessary device register values.

>>> plo1 = hmc833('d1', 'c5')
>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)
>>> n_int, n_frac, doubler, divide_ratio = plo1.divider_values(1000.0)
>>> plo1.config_frequency_registers(n_int, n_frac)
'W00,00,28,18:HD1:LD1:W00,00,00,20:HD1:LD1:'
>>> n_int, n_frac, doubler, divide_ratio = plo1.divider_values(1004.0)
>>> plo1.config_frequency_registers(n_int, n_frac)
'W00,00,28,18:HD1:LD1:W28,f5,c3,20:HD1:LD1:'
>>> n_int, n_frac, doubler, divide_ratio = plo1.divider_values(4207.0)
>>> plo1.config_frequency_registers(n_int, n_frac)
'W00,00,2a,18:HD1:LD1:W11,eb,85,20:HD1:LD1:'
>>> n_int, n_frac, doubler, divide_ratio = plo2.divider_values(4207.0)
>>> plo2.config_frequency_registers(n_int, n_frac)
'W00,00,21,18:HD2:LD2:Wa7,ef,9e,20:HD2:LD2:'
config_gain() → str[source]

Configure current buf_gain and div_gain settings.

Returns:

A command string to configure the device gain settings.

See also

config_vco_registers()

>>> plo1 = hmc833('d1', 'c5')
>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)
>>> plo1.device_initialize(1000.0)
'W00,00,20,00:HD1:LD1:W00,00,02,08:HD1:LD1:W00,00,01,10:HD1:LD1:W00,01,88,28:HD1:LD1:W00,16,28,28:HD1:LD1:W00,60,A0,28:HD1:LD1:W00,01,10,28:HD1:LD1:W00,08,98,28:HD1:LD1:W00,00,00,28:HD1:LD1:W03,07,CA,30:HD1:LD1:W15,B2,64,48:HD1:LD1:W00,21,4d,38:HD1:LD1:WC1,BE,FF,40:HD1:LD1:W00,20,46,50:HD1:LD1:W07,C0,61,58:HD1:LD1:W00,00,C1,78:HD1:LD1:W00,00,28,18:HD1:LD1:W00,00,00,20:HD1:LD1:'
>>> plo2.device_initialize(1000.0)
'W00,00,20,00:HD2:LD2:LB5:W00,00,02,08:HD2:LD2:W00,00,04,10:HD2:LD2:W00,01,88,28:HD2:LD2:W00,16,28,28:HD2:LD2:W00,60,A0,28:HD2:LD2:W00,01,10,28:HD2:LD2:W00,08,98,28:HD2:LD2:W00,00,00,28:HD2:LD2:W03,07,CA,30:HD2:LD2:W19,32,64,48:HD2:LD2:W00,21,4d,38:HD2:LD2:WC1,BE,FF,40:HD2:LD2:W00,40,46,50:HD2:LD2:W07,C0,61,58:HD2:LD2:W00,00,C1,78:HD2:LD2:W00,00,20,18:HD2:LD2:W00,00,00,20:HD2:LD2:'
>>> plo1.auto_gain(1000.0)
>>> plo2.auto_gain(1000.0)
>>> plo1.config_gain()
'W00,81,10,28:HD1:LD1:'
>>> plo2.config_gain()
'W00,81,10,28:HD2:LD2:'
>>> plo2.auto_gain(3817.0)
>>> plo2.config_gain()
'W00,41,10,28:HD2:LD2:'
>>> plo2.buf_gain = hmc833.OutputBufferGain.MAXGAIN
>>> plo2.config_gain()
'W00,61,10,28:HD2:LD2:'
>>> plo2.buf_gain = hmc833.OutputBufferGain.MAXGAIN_MINUS_3DB
>>> plo2.config_gain()
'W00,41,10,28:HD2:LD2:'
config_reference_divider() → str[source]

Configure the reference divider value.

Returns:

The command string required to set the reference divider value.

>>> plo1 = hmc833('d1', 'c5')
>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)
>>> plo1.config_reference_divider()
'W00,00,01,10:HD1:LD1:'
>>> plo2.config_reference_divider()
'W00,00,04,10:HD2:LD2:'
config_refsrc() → str[source]

Configure the reference source.

Returns:

The command string required to set the reference source switch.

>>> plo1 = hmc833('d1', 'c5')
>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)
>>> plo1.config_refsrc()
''
>>> plo2.config_refsrc()
'LB5:'
config_spi_chipen() → str[source]

Configure device to accept the SPI power down command.

Returns:

The command required to reset the device via the SPI.

Note

From the HMC833 data sheet: It is possible to ignore the CEN pin, by clearing rst_chipen_pin_select (Reg_01h[0]=0). Control of Power Down Mode then comes from the serial port register rst_chipen_from_spi, Reg_01h[1].

>>> plo1 = hmc833('d1', 'c5')
>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)
>>> plo1.config_spi_chipen()
'W00,00,02,08:HD1:LD1:'
>>> plo2.config_spi_chipen()
'W00,00,02,08:HD2:LD2:'
config_vco_divider(out_div: int) → str[source]

Configure the VCO output divider.

Parameters:

out_div (int) – The required VCO divider value.

Returns:

The command string required to configure the specified VCO divide value.

Note

This method may also be used to configure the VCO divider and output buffer gains. The gain values must have been previously set using buf_gain() and/or div_gain(). The out_div parameter should be set to the currently configured VCO divide value (available internally as self.__divide_ratio).

config_vco_doubler(doubler: bool) → str[source]

Configure the VCO output frequency doubler.

Parameters:

doubler (bool) – True to activate the frequency doubler, False to deactivate it.

Returns:

The command string required to configure the specified VCO frequency doubler state.

Note

This method may also be used to mute the VCO output. The VCO mute state must have been previously set using mute_vco(). The doubler parameter should be set to the currently configured VCO frequency doubler state (available internally as self.__doubler).

config_vco_mute() → str[source]

Enable or disable VCO output while maintaining PLL/VCO lock.

The mute function provides over 40 dB of isolation throughout the operating range of the HMC833LP6GE.

Returns:

The command string to effect the currently set mute state.

>>> plo1 = hmc833('d1', 'c5')
>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)
>>> plo1.device_initialize(1000.0)
'W00,00,20,00:HD1:LD1:W00,00,02,08:HD1:LD1:W00,00,01,10:HD1:LD1:W00,01,88,28:HD1:LD1:W00,16,28,28:HD1:LD1:W00,60,A0,28:HD1:LD1:W00,01,10,28:HD1:LD1:W00,08,98,28:HD1:LD1:W00,00,00,28:HD1:LD1:W03,07,CA,30:HD1:LD1:W15,B2,64,48:HD1:LD1:W00,21,4d,38:HD1:LD1:WC1,BE,FF,40:HD1:LD1:W00,20,46,50:HD1:LD1:W07,C0,61,58:HD1:LD1:W00,00,C1,78:HD1:LD1:W00,00,28,18:HD1:LD1:W00,00,00,20:HD1:LD1:'
>>> plo1.config_vco_mute()
'W00,01,88,28:HD1:LD1:W00,08,98,28:HD1:LD1:'
config_vco_registers(out_div: int, doubler: bool) → str[source]

Configure VCO registers for the specified divide ratio/doubler.

Parameters:

  • out_div (int) – The specified output divide ratio. This should be in the range 1..62 although only the values in [1] + hmc833.DIVIDER_VALUES are legal.

  • doubler (bool) – True if the output frequency doubler should be enabled, False if the doubler should be disabled.

Returns:

The commands required to set the necessary VCO register values.

>>> plo1 = hmc833('d1', 'c5')
>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)

>>> n_int, n_frac, doubler, divide_ratio = plo1.divider_values(1000.0)
>>> plo1.config_vco_registers(divide_ratio, doubler)
'W00,01,10,28:HD1:LD1:W00,08,98,28:HD1:LD1:W00,00,00,28:HD1:LD1:'

>>> n_int, n_frac, doubler, divide_ratio = plo1.divider_values(1004.0)
>>> plo1.config_vco_registers(divide_ratio, doubler)
''

>>> n_int, n_frac, doubler, divide_ratio = plo1.divider_values(4207.0)
>>> plo1.config_vco_registers(divide_ratio, doubler)
'W00,00,90,28:HD1:LD1:W00,00,18,28:HD1:LD1:W00,00,00,28:HD1:LD1:'

>>> n_int, n_frac, doubler, divide_ratio = plo2.divider_values(4207.0)
>>> plo2.config_vco_registers(divide_ratio, doubler)
'W00,00,90,28:HD2:LD2:W00,00,18,28:HD2:LD2:W00,00,00,28:HD2:LD2:'
property cp_gain: int

The charge pump gain setting.

device_initialize(fout: float) → str[source]

Configure the PLL after power up.

Parameters:

fout (float) – The initial output frequency in MHz.

Returns:

The command string required to effect the device initialization.

To configure the PLL after power up:

  1. Configure the reference divider (write to Reg_02h), if required.

  2. Configure the delta-sigma modulator (write to Reg_06h).

    • Configuration involves selecting the mode of the delta-sigma modulator (Mode A or Mode B), selection of the delta-sigma modulator seed value, and configuration of the delta-sigma modulator clock scheme. It is recommended to use the values found in the Hittite PLL evaluation board control software register files.

  3. Configure the charge pump current and charge pump offset current (write to Reg_09h)

  4. Configure the VCO Subsystem (write to Reg_05h, for more information see section 1.19, and 3.0 VCO Subsystem Register Map. Detailed writes to the VCO subsystem via PLL Reg_05h at start-up are available in the Register Setting Files found in the Hittite PLL Evaluation Software

  5. Configure the VCO output divider/doubler, if needed in the VCO subsystem via PLL Reg_05h.

  6. Program the frequency of operation

    • Program the integer part (write to Reg_03h)

    • Program the fractional part (write to Reg_04h)

Once the HMC833LP6GE is configured after startup, in most cases the user only needs to change frequencies by writing to Reg_03h integer register, Reg_04h fractional register, and Reg_05h to change the VCO output divider or doubler setting if needed, and possibly adjust the charge pump settings by writing to Reg_09h.

>>> plo1 = hmc833('d6', 'd7')
>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)
>>> plo1.device_initialize(1000.0)
'W00,00,20,00:HD6:LD6:W00,00,02,08:HD6:LD6:W00,00,01,10:HD6:LD6:W00,01,88,28:HD6:LD6:W00,16,28,28:HD6:LD6:W00,60,A0,28:HD6:LD6:W00,01,10,28:HD6:LD6:W00,08,98,28:HD6:LD6:W00,00,00,28:HD6:LD6:W03,07,CA,30:HD6:LD6:W15,B2,64,48:HD6:LD6:W00,21,4d,38:HD6:LD6:WC1,BE,FF,40:HD6:LD6:W00,20,46,50:HD6:LD6:W07,C0,61,58:HD6:LD6:W00,00,C1,78:HD6:LD6:W00,00,28,18:HD6:LD6:W00,00,00,20:HD6:LD6:'
>>> plo1.device_initialize(3409.0)
'W00,00,20,00:HD6:LD6:W00,00,02,08:HD6:LD6:W00,00,01,10:HD6:LD6:W00,01,88,28:HD6:LD6:W00,16,28,28:HD6:LD6:W00,60,A0,28:HD6:LD6:W00,00,90,28:HD6:LD6:W00,00,18,28:HD6:LD6:W00,00,00,28:HD6:LD6:W03,0F,4A,30:HD6:LD6:W55,B2,64,48:HD6:LD6:W00,21,4d,38:HD6:LD6:WC1,BE,FF,40:HD6:LD6:W00,20,46,50:HD6:LD6:W07,C0,61,58:HD6:LD6:W00,00,C1,78:HD6:LD6:W00,00,22,18:HD6:LD6:W17,0a,3d,20:HD6:LD6:'
>>> plo2.device_initialize(1000.0)
'W00,00,20,00:HD2:LD2:LB5:W00,00,02,08:HD2:LD2:W00,00,04,10:HD2:LD2:W00,01,88,28:HD2:LD2:W00,16,28,28:HD2:LD2:W00,60,A0,28:HD2:LD2:W00,01,10,28:HD2:LD2:W00,08,98,28:HD2:LD2:W00,00,00,28:HD2:LD2:W03,07,CA,30:HD2:LD2:W19,32,64,48:HD2:LD2:W00,21,4d,38:HD2:LD2:WC1,BE,FF,40:HD2:LD2:W00,40,46,50:HD2:LD2:W07,C0,61,58:HD2:LD2:W00,00,C1,78:HD2:LD2:W00,00,20,18:HD2:LD2:W00,00,00,20:HD2:LD2:'
>>> plo2.device_initialize(2791.0)
'W00,00,20,00:HD2:LD2:LB5:W00,00,02,08:HD2:LD2:W00,00,04,10:HD2:LD2:W00,01,88,28:HD2:LD2:W00,16,28,28:HD2:LD2:W00,60,A0,28:HD2:LD2:W00,00,90,28:HD2:LD2:W00,08,98,28:HD2:LD2:W00,00,00,28:HD2:LD2:W03,0F,4A,30:HD2:LD2:W59,32,64,48:HD2:LD2:W00,21,4d,38:HD2:LD2:WC1,BE,FF,40:HD2:LD2:W00,40,46,50:HD2:LD2:W07,C0,61,58:HD2:LD2:W00,00,C1,78:HD2:LD2:W00,00,2c,18:HD2:LD2:Wa7,ef,9e,20:HD2:LD2:'
property div_gain: DividerGain

The divider output stage gain setting.

divider_values(fout: float) → Tuple[int, int, bool, int][source]

Calculate the N divider values.

Parameters:

fout (float) – The desired output frequency in MHz.

Returns:

A tuple containing the parameters for the fractional frequency tuning: (n_int, n_frac, doubler, divider) where:

n_int: is the integer division ratio, a number between 20 and 524,284.

n_frac : is the fractional part, from 0 to 2^24.

doubler : is True if the frequency doubler must be enabled, False if the frequency doubler should be disabled.

divider : the required setting for the output frequency divider. If this is 1 then the divider is not used.

Raises:

FrequencyRangeException If the specified output frequency is out of range.

>>> plo1 = hmc833('d1', 'c5')
>>> plo1.divider_values(762)
(30, 8053064, False, 2)
>>> plo1.divider_values(1762)
(35, 4026532, False, 1)
>>> plo1.divider_values(3762)
(37, 10401874, True, 1)
>>> plo1.divider_values(5762)
(57, 10401874, True, 1)
>>> plo1.divider_values(6762)
Traceback (most recent call last):
   ...
FrequencyRangeException
>>> plo1.divider_values(20)
Traceback (most recent call last):
   ...
FrequencyRangeException
enable_sd_modulator(en: bool) → str[source]

Configure the PLO sigma/delta modulator.

Parameters:

en (bool) – True for enabling the SD modulator. False to disable.

Returns:

The command string required to effect the register initialization.

property fref: float

The current input reference frequency in MHz.

Note that this will set the value of the fref property only. Updating the PLO hardware should be done separately. See, for example, config_reference_divider().

Note also that if fref or refdiv are changed then the PLO output frequency tuning must also be updated. This can be done by calling:

plo.config_frequency(fout, full_reg_update=True)

See also

HMC833Controller.configure_refdiv() and HMC833Controller.configure_refsrc().

init_registers(nint: int, nfrac: int, out_div: int, doubler: bool = False) → str[source]

Initialize the frequency, SD modulator and VCO subsystem registers.

Parameters:

  • nint (19-bit int) – The integer part of the frequency tuning.

  • nfrac (24-bit int) – The fractional part of the frequency tuning.

  • out_div (5-bit int) – The RF output divider value.

  • doubler (bool) – Enables or disables the output frequency doubler.

Returns:

The command string required to effect the register initialization.

Note

The synthesizer output frequency is controlled by the following registers:

  • Frequency register, integer part, Reg_03h[18:0]

  • Frequency register, fractional part, Reg_04h[23:0]

The SD modulator is configured by the following:

  • Fractional bypass, Reg_06h[7]

  • SD enable, Reg_06h[11]

The VCO subsystem registers are accessed via Reg_05h. Reg_05h is a special register used for indirect addressing of the VCO subsystem. Writes to Reg_05h are automatically forwarded to the VCO subsystem by the VCO SPI state machine controller.

  • Reg_05h[2:0] holds the VCO subsystem address: 0b000

  • Reg_05h[6:3] is the VCO subsystem register address

  • Reg_05h[15:7] is the data to be written to the VCO register

The VCO subsystem registers control the following:

  • RF divide ratio, VCO_Reg_02h[5:0]

  • RF output buffer gain control, VCO_Reg_02h[7:6]

  • Divider output stage gain control, VCO_Reg_02h[8]

  • Fundamental/doubler mode selection, VCO_Reg_03h[0]

  • RF buffer bias, VCO_Reg_03h[4:3]

>>> plo1 = hmc833('d1', 'c5')
>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)
>>> plo1.init_registers(*plo1.divider_values(1000.0))
'W03,07,CA,30:HD1:LD1:W15,B2,64,48:HD1:LD1:W00,21,4d,38:HD1:LD1:WC1,BE,FF,40:HD1:LD1:W00,20,46,50:HD1:LD1:W07,C0,61,58:HD1:LD1:W00,00,C1,78:HD1:LD1:'
>>> plo2.init_registers(*plo2.divider_values(4207.0))
'W03,0F,4A,30:HD2:LD2:W59,32,64,48:HD2:LD2:W00,21,4d,38:HD2:LD2:WC1,BE,FF,40:HD2:LD2:W00,40,46,50:HD2:LD2:W07,C0,61,58:HD2:LD2:W00,00,C1,78:HD2:LD2:'
init_vco_registers() → str[source]

Initialize VCO registers 4 and 5.

This initialization can be done once at device power up or reset.

Returns:

The command required to initialize VCO_Reg_04h and VCO_Reg_05h.

>>> plo1 = hmc833('d1', 'c5')
>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)
>>> plo1.init_vco_registers()
'W00,01,88,28:HD1:LD1:W00,16,28,28:HD1:LD1:W00,60,A0,28:HD1:LD1:'
>>> plo2.init_vco_registers()
'W00,01,88,28:HD2:LD2:W00,16,28,28:HD2:LD2:W00,60,A0,28:HD2:LD2:'
property mute_vco: bool

The synthesizer output mute setting. Set to False to enable RF output, True to mute the output.

Note that this will set the value of the mute_vco property only. Updating the PLO hardware should be done separately. See, for example, config_vco_mute().

pin_config() → str[source]

Initialize controller pin configuration.

Returns:

A string specifying the commands required to initialize the connected controller pins.

>>> plo1 = hmc833('d1', 'c5', fref=50.0)
>>> plo2 = hmc833('d2', 'c6', 'b5', fref=250.0, refdiv=4,
...     refsrc=hmc833.ReferenceSource.EXTERNAL)
>>> plo1.pin_config()
'OD1:LD1:IC5:W00:'
>>> plo2.pin_config()
'OD2:LD2:IC6:OB5:LB5:W00:'
property refdiv: int

The current reference frequency divider value.

Note that this will set the value of the refdiv property only. Updating the PLO hardware should be done separately. See, for example, config_reference_divider().

Note also that if fref or refdiv are changed then the PLO output frequency tuning must also be updated. This can be done by calling:

plo.config_frequency(fout, full_reg_update=True)

See also

HMC833Controller.configure_refdiv() and HMC833Controller.configure_refsrc().

property refsrc: ReferenceSource

The current reference source.