ad9552

class rfblocks.ad9552(cs: str | None = None, lockdetect: str | None = None, reset: str | None = None, fref: float = 20.0, refselect: str | None = None, refsrc: ReferenceSource = ReferenceSource.INTERNAL)[source]

Encapsulates control of the AD9552 clock generator.

Documentation for the clock generator rfblocks module which uses the AD9552 can be found here: A Low Jitter Variable Rate Clock Generator to 1000 MHz

Parameters:

cs (str, optional) – The AD9552 chip select (~CS) controller pin.
lockdetect (str, optional) – The AD9552 lock detect (LOCKED) controller pin.
reset (str, optional) – The AD9552 reset (RESET) controller pin.
fref (float) – The input reference frequency in MHz.
refselect (str, optional) – Select either external or on board reference source. This facility is only available on version 3 (or greater) of the board hardware.

class CmosPolarity(value)[source]: An enum containing the possible CMOS clock mode polarities. (ad9552.CmosPolarity.DIFF_POS, ad9552.CmosPolarity.COMM_POS, ad9552.CmosPolarity.COMM_NEG, ad9552.CmosPolarity.DIFF_NEG)

class DriveStrength(value)[source]: An enum containing the possible clock drive strengths. (ad9552.DriveStrength.WEAK, ad9552.DriveStrength.STRONG)

OUT1 = 1: Clock channel 1 identifier

OUT2 = 2: Clock channel 2 identifier

class OutputMode(value)[source]: An enum containing the possible clock output modes. (ad9552.OutputMode.CMOS_BOTH_ACTIVE, ad9552.OutputMode.CMOS_POS_ACTIVE, ad9552.OutputMode.CMOS_NEG_ACTIVE, ad9552.OutputMode.CMOS_TRISTATE, ad9552.OutputMode.LVDS, ad9552.OutputMode.LVPECL)

class OutputModeControl(value)[source]: An enum containing the possible clock output mode control types. (ad9552.OutputModeControl.PIN, ad9552.OutputModeControl.SPI)

class OutputState(value)[source]: An enum containing the possible clock output states. (ad9552.OutputState.ACTIVE, ad9552.OutputState.POWERED_DOWN)

P0_VALUES = [4, 5, 6, 7, 8, 9, 10, 11]: Legal P0 output divider values

P1_VALUES = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63]: Legal P1 output divider values

class ReferenceSource(value)[source]: An enum containing the possible settings for the reference source. (ad9552.ReferenceSource.INTERNAL, ad9552.ReferenceSource.EXTERNAL)

class SourceControl(value)[source]: An enumeration.

VCO_MAX = 4050: The maximum internal VCO frequency

VCO_MIN = 3350: The minimum internal VCO frequency

calibrate_vco() → str[source]

Request VCO calibration.

Returns:: The command string required to initiate VCO calibration.

Note

The process calibrating the VCO must be carried out after each update of the clock output frequency. Note that this must be done after updating the PLL control registers. SPI control of VCO calibration must have been enabled prior to issuing this command.

This method is used internally by the various ad9552 class methods and may be useful if sub-classing to add extra functionality.

>>> clk1 = ad9552('d0', 'c4', 'c5')
>>> clk1.calibrate_vco()
'LD0:W00,0E,F4:HD0:LD0:W00,05,01:HD0:'

check_is_locked() → str[source]

Check if the device PLL is locked.

Returns:: The command string for checking the device PLL lock status.

>>> clk1 = ad9552('d2', 'c6', 'c7')
>>> clk1.check_is_locked()
'PC6:'

chip_reset() → str[source]

Reset the chip internal logic to default states.

Returns:: The command string required to reset the device or the empty string if there is no device reset pin connected to the controller.

>>> clk2 = ad9552('d2', 'c6', 'c7', fref=20.0)
>>> clk2.chip_reset()
'HC7:LC7:'

config_output_frequency(pll_values: Tuple[int, int, float, float, int, int]) → str[source]

Configure and update the output frequency.

Parameters:: pll_values (tuple) – The PLL control values required to produce the desired output frequency.
Returns:: The string command required to configure the current device PLL control registers and update the output frequency.

The required command sequence runs as follows:

Enable SPI control of VCO calibration.
Update the PLL control registers
Request VCO calibration.

Note that ‘streaming’ mode is used to convey the PLL control register values to the device. See the section Operation of the Serial Control Port in the AD9552 datasheet (Rev E., pp20-22).

>>> clk1 = ad9552('d2', 'c6', 'c7', fref=10.0)
>>> clk1.config_output_frequency(clk1.divider_values(644.53125))
'LD2:W00,1D,04:HD2:LD2:W00,0E,74:HD2:LD2:W00,05,01:HD2:LD2:W60,19,80,0A,90,FE,5B,08,FC,FF,C1:HD2:LD2:W00,05,01:HD2:LD2:W00,0E,F4:HD2:LD2:W00,05,01:HD2:'
>>> clk1.config_output_frequency(clk1.divider_values(100))
'LD2:W00,1D,04:HD2:LD2:W00,0E,74:HD2:LD2:W00,05,01:HD2:LD2:W60,19,80,39,00,00,00,FE,FF,FF,AF:HD2:LD2:W00,05,01:HD2:LD2:W00,0E,F4:HD2:LD2:W00,05,01:HD2:'

config_output_mode(chan: int, mode: OutputMode, state: OutputState, strength: DriveStrength = DriveStrength.STRONG, polarity: CmosPolarity = CmosPolarity.DIFF_POS, enabled: OutputModeControl = OutputModeControl.SPI) → str[source]

Configure the clock output mode for a specified clock channel.

Parameters:

chan (int) – The specified clock channel. This must be one of ad9552.OUT1 or ad9552.OUT2.
mode (ad9552.OutputMode) –
state (ad9552.OutputState) –
strength (ad9552.DriveStrength, optional) –
polarity (ad9552.CmosPolarity, optional) –
enabled (ad9552.OutputModeControl, optional) –

Returns:

The command string required to configure the specified output mode for the specified clock channel. If an illegal clock channel is specified, and empty command string is returned.

>>> clk1 = ad9552('d2', 'c6', 'c7', fref=20.0)
>>> clk1.config_output_mode(
...     ad9552.OUT1,
...     ad9552.OutputMode.LVDS,
...     ad9552.OutputState.ACTIVE,
...     ad9552.DriveStrength.STRONG,
...     ad9552.CmosPolarity.DIFF_POS)
'LD2:W00,32,A1:HD2:LD2:W00,05,01:HD2:'
>>> clk1.config_output_mode(
...     ad9552.OUT2,
...     ad9552.OutputMode.LVPECL,
...     ad9552.OutputState.ACTIVE,
...     ad9552.DriveStrength.STRONG,
...     ad9552.CmosPolarity.DIFF_POS)
'LD2:W00,34,A9:HD2:LD2:W00,05,01:HD2:'
>>> clk1.config_output_mode(
...     ad9552.OUT1,
...     ad9552.OutputMode.LVDS,
...     ad9552.OutputState.POWERED_DOWN,
...     ad9552.DriveStrength.STRONG,
...     ad9552.CmosPolarity.DIFF_POS)
'LD2:W00,32,E1:HD2:LD2:W00,05,01:HD2:'

config_reference_multiplier() → str[source]

Enable the input reference multiplier.

Returns:: The command string required to set the input reference multiplier.

>>> clk1 = ad9552('d0', 'c4', 'c5')
>>> clk1.config_reference_multiplier()
'LD0:W00,1D,04:HD0:'

config_refsrc() → str[source]

Set the state of the reference select controller pin based on whether an external reference source is being used.

Returns:: The command string required to set the state of the reference select controller pin.

>>> clk1 = ad9552('d0', 'c4', 'c5', refselect='b1')
>>> clk1.config_refsrc()
'OB1:HB1:'
>>> clk1.refsrc = ad9552.ReferenceSource.EXTERNAL
>>> clk1.config_refsrc()
'OB1:LB1:'

config_src_control(src: SourceControl) → str[source]

Configure the source for channel 2.

Parameters:: src (ad9552.SourceControl) –
Returns:: The string command required to configure the specified source for channel 2.

>>> clk1 = ad9552('d2', 'c6', 'c7', fref=20.0)
>>> clk1.config_src_control(ad9552.SourceControl.PLL)
'LD2:W00,33,00:HD2:LD2:W00,05,01:HD2:'
>>> clk1.config_src_control(ad9552.SourceControl.REF)
'LD2:W00,33,08:HD2:LD2:W00,05,01:HD2:'

divider_values(fout: float) → Tuple[int, int, float, float, int, int][source]

Calculate the required device divider values.

Parameters:

fout (float) – The desired output frequency (in MHz)

Returns:

A tuple containing: (K, N, FRAC, MOD, P0, P1) or None if there was no divider solution obtained for the specified output frequency. See the sections Output/Input Frequency Relationship and Calculating Divider Values in the AD9552 datasheet (Rev E., pp17-18).

K : Reference frequency multiplier (either 1 or 2)

NThe 8-bit integer divide value for the SDM.: Note that operational limitations impose a lower boundary of 64 (0x40) on N.

FRAC : The 20-bit fractional part of the SDM.

MOD : The 20-bit modulus of the SDM.

P0, P1 : Output divider values

>>> clk1 = ad9552('d0', 'c4', 'c5')
>>> clk1.divider_values(50.0)
(1, 170, 0, 1048575, 4, 17)
>>> clk1.divider_values(125.0)
(1, 168, 786429, 1048572, 9, 3)
>>> clk1.divider_values(250.0)
(1, 175, 0, 1048575, 7, 2)
>>> clk1.divider_values(644.53125)
(1, 193, 376809, 1048512, 6, 1)
>>> clk2 = ad9552('d2', 'c6', 'c7', fref=10.0)
>>> clk2.divider_values(50.0)
(2, 170, 0, 1048575, 4, 17)
>>> clk2.divider_values(11.0)
(2, 167, 786429, 1048572, 5, 61)
>>> clk2.divider_values(12.0)
Traceback (most recent call last):
   ...
DividerRangeException: No valid P1 value

enable_vco_calibration() → str[source]

Enable SPI control of VCO calibration.

Returns:: The command string required to enable SPI control of VCO calibration.

Note

The process of enabling SPI control of VCO calibration must be carried out before each update of the clock output frequency. Note that this must be done before updating the PLL control registers.

This method is used internally by the various ad9552 class methods and may be useful if sub-classing to add extra functionality.

>>> clk1 = ad9552('d0', 'c4', 'c5')
>>> clk1.enable_vco_calibration()
'LD0:W00,0E,74:HD0:LD0:W00,05,01:HD0:'

pin_config() → str[source]

Initialize controller pin configuration.

Returns:: The command string required to configure the device controller pins.

>>> clk1 = ad9552('d0', 'c4', 'c5', fref=26.0)
>>> clk1.pin_config()
'OD0:HD0:IC4:OC5:LC5:'

property refsrc: ReferenceSource: The current reference source.

register_ioupdate() → str[source]

Perform a device register update.

Returns:: The command string required to perform a device register update.

Note

Data from a write sequence is stored in a buffer register (data inactive). An active register exists for every buffer register. The I/O update signal is used to transfer the contents from the buffer register into the active register.

This method is used internally by the various ad9552 class methods and may be useful if sub-classing to add extra functionality.

>>> clk1 = ad9552('d0', 'c4', 'c5')
>>> clk1.register_ioupdate()
'LD0:W00,05,01:HD0:'