Open RF Prototyping

A Low Phase Noise Reference Clock

Features

  • Stable 100MHz reference clock.

  • Very low phase noise: -145 dBc/Hz at 1 kHz offset (100 MHz carrier).

  • Selectable on-board or external 10 MHz reference.

  • Nominal 8 dBm output power.

Typical Performance Characteristics

Phase noise

Figure 1: Phase noise of 100MHz ABLNO VCXO as given in the Abracon ABLNO evaluation board documentation.

Application Information

Board connector configuration

Table 1. Board pin configuration and function descriptions

Board Pin

Type

Description

Ref. Src.

Input

Clock reference select signal

Locked

Output

Lock detect output, CMOS drive

D0, D1

Input

Integer-N division ratio selection

5V

Power Input

5V DC power input

GND

Power Input

Module ground

Ref. In

Signal Input

External 10MHz reference input signal

Vco Out

Signal Output

100MHz reference clock signal output

Vtune

Signal Output

Optional charge pump signal output
Conn. layout

Figure 2: Reference clock connector layout.

Design Notes

Schematic design

Figure 3: Reference clock schematic design.